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ASAHI KASEI
[AK4702EQ]
AK4702EQ
2ch DAC with AV SCART switch
GENERAL DESCRIPTION The AK4702 offers the ideal features for digital set-top-box systems. Using AKM's multi-bit architecture for its modulator, the AK4702 delivers a wide dynamic range while preserving linearity for improved THD+N performance. The AK4702 integrates a combination of SCF and CTF filters, removing the need for high cost external filters and increasing performance for systems with excessive clock jitter. The AK4702 also including the audio switches and volumes designed primarily for digital set-top-box systems. The AK4702 is offered in a space saving 48-pin LQFP package. FEATURES DAC Sampling Rates Ranging from 8kHz to 50kHz 18bit 8x FIR Digital Filter 2nd order Analog LPF On chip Buffer with Single-ended Output Digital de-emphasis for 32k, 44.1k and 48kHz sampling I/F format: 18bit MSB justified, 18/16bit LSB justified, I2S Master clock: 256fs, 384fs High Tolerance to Clock Jitter Analog switches for SCART Audio section THD+N: -86dB (@2Vrms) Dynamic Range: 96dB (@2Vrms) Stereo Analog Volume with Zero-cross Detection Circuit (+6dB to -60dB & Mute) Five Analog Inputs Two Stereo Input (TV, VCR SCART) One Mono Input for Tone Five Analog Outputs Two Stereo Outputs (TV, VCR SCART) One Mono Output Loop-through mode for standby Pop Noise Free Circuit for Power on/off Video section 75ohm driver 6dB Gain for Outputs Adjustable gain Four CVBS/Y inputs (ENCx2, TV, VCR), Three CVBS/Y output (RF, TV, VCR) Three R/C inputs (ENCx2, VCR), Two R/C output (TV, VCR) Bi-directional control for VCR-Chroma/Red Two G and B inputs (ENC, VCR), One G and B outputs (TV) Power supply 5V+/-5% and 12.6V~10V Low Power Dissipation Package Small 48pin LQFP
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ASAHI KASEI
[AK4702EQ]
MONOOUT MONOIN -6dB/0dB/2.44dB VOL
MCLK TVOUTL
DAC
BICK LRCK SDATA
TVOUTR
Volume #0 TV1/0 VCRINL VCRINR
Volume #1 +6 to -60dB (2dB/step)
MONO
VCROUTL TVINL
VCROUTR TVINR Bias (Mute) VCOM5 VCR1/0 VCOM12 SCK SDA PDN Register Control VD VP VSS
Audio Block
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ASAHI KASEI
[AK4702EQ]
( Typical connection )
VVD1 VVD2 VVSS 6dB RFV
( Typical connection ) RF Mod
ENC CVBS/Y ENC Y VCR CVBS/Y TV CVBS
ENCV ENCY VCRVIN TVVIN 0, 1, 2, 3dB 6dB TVVOUT
ENC R/C ENC C VCR R/C
ENCRC ENCC VCRRC 6dB TVRC TV SCART
ENC G/CVBS VCR G
ENCG VCRG 6dB TVG
ENC B VCR B
ENCB VCRB 6dB TVB
6dB
VCRVOUT
VCR SCART
6dB VCRC
Video Block
( Typical connection ) VCR FB VCRFB 2V 0V 6dB TVFB
( Typical connection )
TV SCART
0/ 6/ 12V
TVSB
VCRSB 0/ 6/ 12V
VCR SCART
Monitor
INT
Video Blanking Block
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ASAHI KASEI
[AK4702EQ]
Ordering Guide
AK4702EQ -10 +70C 48pin LQFP (0.5mm pitch)
Pin Layout
VCRVOUT
MCLK
LRCK
TVFB
BICK
SDTI
PDN
SDA
RFV
SCL
VD 38
48
47
46
45
44
43
42
41
40
39
37 36 35 34
VSS
VCRC VVSS TVVOUT VVD2 TVRC TVG TVB VVD1 ENCB ENCG ENCRC ENCC
1 2 3 4 5 6 7 8 9 10 11 12 13 15 16 19 20 21 14 17 18 22 23 24 Top View
PVCOM DVCOM VP MONOOUT TVOUTL TVOUTR VCROUTL VCROUTR MONOIN TVINL TVINR VCRINL
AK4702EQ
33 32 31 30 29 28 27 26 25
VCRVIN
VCRSB
TVVIN
VCRG
ENCV
VCRB
Compatibility with AK4702
AK4702 -60dB -/+3%, -/+3deg (min/max) AK4702EQ 0.4%, 0.8deg (typ)
THD+N at 3Vrms output DG, DP
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INT
VCRINR
VCRRC
VCRFB
ENCY
TVSB
2005/09
ASAHI KASEI
[AK4702EQ]
PIN/FUNCTION
No. 1 2 3 4 Pin Name VCRC VVSS TVVOUT VVD2 I/O O O Function Chrominance Output Pin for VCR Video Ground Pin. 0V. Composite/Luminance Output Pin for TV Video Power Supply Pin #2. 5V Normally connected to VVSS with a 0.1F ceramic capacitor in parallel with a 10F electrolytic cap. Red/Chrominance Output Pin for TV Green Output Pin for TV Blue Output Pin for TV Video Power Supply Pin #1. 5V Normally connected to VVSS with a 0.1F ceramic capacitor in parallel with a 10F electrolytic cap. Blue Input Pin for Encoder Green Input Pin for Encoder Red/Chrominance Input Pin1 for Encoder Chrominance Input Pin2 for Encoder Composite/Luminance Input Pin1 for Encoder Composite/Luminance Input Pin2 for Encoder Composite/Luminance Input Pin for TV Composite/Luminance Input Pin for VCR Fast Blanking Input Pin for VCR Red/Chrominance Input Pin for VCR Green Input Pin for VCR Blue Input Pin for VCR Interrupt Pin for Video Blanking Slow Blanking Input/Output Pin for VCR Slow Blanking Output Pin for TV Rch VCR Audio Input Pin Lch VCR Audio Input Pin Rch TV Audio Input Pin Lch TV Audio Input Pin MONO Input Pin Rch Analog Output Pin1 Lch Analog Output Pin1 Rch Analog Output Pin2 Lch Analog Output Pin2 MONO Analog Output Pin Power Supply Pin. 12V Normally connected to VSS with a 0.1F ceramic capacitor in parallel with a 10F electrolytic cap. DAC Common Voltage Pin Normally connected to VSS with a 0.1F ceramic capacitor in parallel with a 10F electrolytic cap. Audio Common Voltage Pin Normally connected to VSS with a 0.1F ceramic capacitor in parallel with a 10F electrolytic cap. The caps affect the settling time of audio bias level.
5 6 7 8
TVRC TVG TVB VVD1
O O O -
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
ENCB ENCG ENCRC ENCC ENCV ENCY TVVIN VCRVIN VCRFB VCRRC VCRG VCRB INT VCRSB TVSB VCRINR VCRINL TVINR TVINL MONOIN VCROUTR VCROUTL TVOUTR TVOUTL MONOOUT VP
I I I I I I I I I I I I O I/O O I I I I I O O O O O -
35
DVCOM
O
36
PVCOM
O
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ASAHI KASEI
[AK4702EQ]
PIN/FUNCTION (Continued)
Ground Pin. 0V. DAC Power Supply Pin. 5V Normally connected to VSS with a 0.1F ceramic capacitor in parallel with a 10F electrolytic cap. 39 MCLK I Master Clock Input Pin An external TTL clock should be input on this pin. 40 BICK I Audio Serial Data Clock Pin 41 SDTI I Audio Serial Data Input Pin 42 LRCK I L/R Clock Pin 43 SCL I Control Data Clock Pin 44 SDA I/O Control Data Pin 45 PDN I Power-Down Mode Pin When at "L", the AK4702 is in the power-down mode and is held in reset. The AK4702 should always be reset upon power-up. 46 RFV O Composite Output Pin for RF modulator 47 VCRVOUT O Composite/Luminance Output Pin for VCR 48 TVFB O Fast Blanking Output Pin for TV Note: All input pins except pull-up/down pin should not be left floating. 37 38 VSS VD -
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ASAHI KASEI
[AK4702EQ]
Internal Equivalent Circuits
Pin No. Pin Name Type Equivalent Circuit Description
VD
39 40 41 42 43 45 MCLK BICK SDTI LRCK SCL PDN
200
Digital IN
VSS
VD 200
44
SDA
Digital I/O
I2C Bus voltage must not exceed VD.
VSS
21
INT
Digital OUT
Normally connected to VD(5V) through 10kohm resister externally.
VSS
46 47 48 1 3 5 6 7
RFV VCROUT TVFB VCRC TVVOUT TVRC TVG TVB
VVD1
VVD2
Video OUT
VVSS
VVSS
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ASAHI KASEI
[AK4702EQ]
Pin No. 9 10 11 12 13 14 15 16 17 18 19 20
Pin Name ENCB ENCG ENCRC ENCC ENCV ENCY TVVIN VCRVIN VCRFB VCRRC VCRG VCRB
Type
Equivalent Circuit
VVD1 200
Description
Video IN
VVSS
VP 200
VP
22 23
VCRSB TVSB
Video SB
(120k) VSS VSS VP VSS
The 120kohm is not attached for TVSB.
24 25 26 27 28
VCRINR VCRINL TVINR TVINL MONOIN
200
Audio IN
VSS VP VP 100
29 30 31 32 33
VCROUTR VCROUTL TVOUTR TVOUTL MONOOU T
Audio OUT
VSS
VSS
VD
VD 100
VD
35 36
DVCOM PVCOM
VCOM OUT
VSS VSS
VSS
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ASAHI KASEI
[AK4702EQ]
ABSOLUTE MAXIMUM RATINGS
(VSS=VVSS=0V;Note: 1) Parameter Power Supply Symbol VD VVD1 VVD2 VP |VSS-VVSS| (Note: 2) IIN VIND VINV VINA Ta Tstg min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -10 -65 max 6.0 6.0 6.0 14 0.3 10 VD+0.3 VVD1+0.3 VP+0.3 70 150 Units V V V V V mA V V V C C
Input Current (any pins except for supplies) Input Voltage Video Input Voltage Audio Input Voltage Ambient Operating Temperature Storage Temperature Note: 1. All voltages with respect to ground. Note: 2. VSS and VVSS must be connected to the same analog ground plane.
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS=VVSS=0V; Note: 1) Parameter Power Supply Symbol VD VVD1 VVD2 VP Note: 3. Analog output voltage scales with the voltage of VD. AOUT (typ@0dB) = 2Vrms x VD/5. min 4.75 4.75 VVD1 10 typ 5.0 5.0 5.0 12 max 5.25 VVD2 5.25 12.6 Units V V V V
*AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
ELECTRICAL CHARACTERISTICS (Ta = 25C; VP=12V, VD = 5V; VVD1=VVD2 = 5V; fs = 48kHz; BICK = 64fs) Power Supplies Power Supply Current Normal Operation (PDN = "H"; Note: 4) VD VVD1+VVD2 VP Power-Down Mode (PDN = "L"; Note: 5) VD VVD1+VVD2 VP
14 20 5 10 10 10
30 40 10 100 100 100
mA mA mA A A A
Note: 4. STBY bit ="L", All video outputs active. No signal, no load for A/V switches. fs=48kHz "0"data input for DAC. Note: 5. All digital inputs including clock pins (MCLK, BICK and LRCK) are held at VD or VSS.
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ASAHI KASEI
[AK4702EQ]
DIGITAL CHARACTERISTICS (Ta = 25C; VD = 4.75 5.25V) Parameter Symbol min High-Level Input Voltage VIH 2.0 Low-Level Input Voltage VIL Low-Level Output Voltage VOL (SDA pin : Iout= 3mA, INT pin : Iout= 1mA) Input Leakage Current Iin -
typ -
max 0.8 0.4 10
Units V V V
-
A
ANALOG CHARACTERISTICS (AUDIO) (Ta = 25C; VP=12V, VD = 5V; VVD1=VVD2 = 5V; fs = 48kHz; BICK = 64fs; Signal Frequency = 1kHz; 18bit Input Data; Measurement frequency = 20Hz 20kHz; RL 4.5k; Volume#0=Volume#1=0dB, 0dB=2Vrms output; unless otherwise specified) Parameter min typ max Units 18 bit DAC Resolution Stereo Input: (TVINL/TVINR/VCRINL/VCRINR pins) Analog Input Characteristics Input Voltage 2 Vrms Input Resistance 100 150 k Mono Input: (MONOIN pin) Analog Input Characteristics Input Voltage 1 Vrms Input Resistance 40 60 k Stereo/Mono Output: (TVOUTL/TVOUTR/VCROUTL/VCROUTR/MONOOUT pins; Note: 6) Analog Output Characteristics Volume#0 Step Width (0dB to -6dB) 6 dB Volume#1 Step Width (+6dB to -12dB) 1.6 2 2.4 dB (-12dB to -40dB) 0.5 2 3.5 dB (-40dB to -60dB) 0.1 2 3.9 dB THD+N (at 2Vrms output. Note: 7) -86 -80 dB Dynamic Range (-60dB Output, A-weighted. Note: 7) 92 96 dB S/N (A-weighted. Note: 7) 92 96 dB Interchannel Isolation (Note: 7, Note: 8) 80 90 dB Interchannel Gain Mismatch (Note: 7, Note: 8) 0.3 dB Gain Drift 200 ppm/C Load Resistance (AC-Lord; Note: 9) TVOUTL/R, VCROUTL/R, MONOOUT 4.5 k Output Voltage (Note: 9, Note: 10) 1.85 2 2.15 Vrms Power Supply Rejection (PSR. Note: 11) 50 dB Note: 6. Measured by Audio Precision System Two Cascade. Note: 7. DAC to TVOUT. Note: 8. Between TVOUTL and TVOUTR with digital inputs 1kHz/0dBFS. Note: 9. THD+N : -80dB(min. at 2Vrns). Note: 10. Full-scale output voltage by DAC (0dBFS). Output voltage of DAC scales with the voltage of VD, Stereo output (typ@0dBFS) = 2Vrms x VD/5 when volume#0=volume#1=0dB. Do not output signals over 3Vrms. Note: 11. The PSR is applied to VD with 1kHz, 100mV.
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ASAHI KASEI
[AK4702EQ]
FILTER CHARACTERISTICS (AUDIO) (Ta = 25C; VP=10.012.6V, VD = 4.755.25V, VVD1=VVD2 = 4.755.25V; fs = 48kHz; DEM0 = "1", DEM1 = "0") Parameter Symbol min typ max Units Digital filter PB 0 21.77 kHz Passband 0.05dB (Note: 12) 24.0 kHz -6.0dB Stopband (Note: 12) SB 26.23 kHz Passband Ripple PR dB 0.06 Stopband Attenuation SA 54 dB Group Delay (Note: 13) GD 19.1 1/fs Digital Filter + LPF FR dB Frequency Response 0 20.0kHz 0.5
Note: 12. The passband and stopband frequencies scale with fs (system sampling rate). ex.) PB=0.4535xfs (@0.05dB), SB=0.546xfs. Note: 13. The calculating delay time which occurred by digital filtering. This time is from setting the 16/18bit data of both channels to input register to the output of analog signal.
ANALOG CHARACTERISTICS (VIDEO) (Ta = 25C; VP=12V, VD = 5V; VVD1=VVD2 = 5V; VVOL1/0= "00" unless specified.) Parameter Conditions min typ Sync tip clamp 0.7 voltage at output Chrominance bias 2.2 voltage at output Gain Input=0.3Vp-p, 100kHz 5.5 6
RGB Gain Input=0.3Vp-p, 100kHz VVOL1/0= "00" VVOL1/0= "01" VVOL1/0= "10" VVOL1/0= "11" Interchannel Gain Mismatch Frequency response Input impedance Input Signal Load Resistance Load Capacitance Dynamic Output Signal Y/C Cross talk S/N Differential Gain Differential Phase Input=0.3Vp-p, 100kHz (Note: 14) Input=0.3Vp-p, Response at 6MHz Chrominance input (internally biased) f=100kHz, maximum with distortion < 1.0%, gain=6dB. Except RFV pin (Note: 15) RFV pin (Note: 16) C1 (Note: 15) C2 (Note: 15, Note: 16) f=100kHz, maximum with distortion < 1.0% f=4.43MHz, 1Vp-p input. Among TVVOUT, TVRC, VCRVOUT and VCRC outputs. Reference Level = 0.7Vp-p, CCIR 567 weighting. BW= 15kHz to 5MHz. 0.7Vpp 5steps modulated staircase. chrominance &burst are 280mVpp, 4.43MHz. 0.7Vpp 5steps modulated staircase. chrominance &burst are 280mVpp, 4.43MHz. 5.5 6.7 7.7 8.6 -0.3 -1 40 150 20k 6 7.2 8.2 9.1 -0.5 60 -
max
Units V V
6.5 6.5 7.7 8.7 9.6 0.3
dB dB dB dB dB dB dB kohm Vpp ohm ohm pF pF Vpp dB dB % Degree
1.5 400 15 3 -
-
-50 74 +0.4 +0.8
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ASAHI KASEI
[AK4702EQ]
Note: 14. TVRC, TVG, TVB. Note: 15. Refer the Figure 1.
R1 75 ohm Video Signal Output C2 max: 15pF C1 max: 400pF R2 75 ohm
Figure 1. Load Resistance R1+R2, and Load Capacitance C1 and C2. Note: 16. AC load. Refer the Figure 2.
Video Signal Output C2 max: 15pF
R1 20k ohm (AC load)
Figure 2. Load Resistance R1 and Load Capacitance C1
SWITCHING CHARACTERISTICS (Ta = 25C; VP=10.0 12.6V, VD = 4.75 5.25V, VVD1=VVD2 = 4.75 5.25V; CL = 20pF) Parameter Symbol Min typ 2.048 fCLK Master Clock Frequency 256fs: 40 dCLK Duty Cycle 3.072 fCLK 384fs: 40 dCLK Duty Cycle fs 8 LRCK Frequency Duty 45 Duty Cycle Audio Interface Timing 312.5 tBCK BICK Period 100 tBCKL BICK Pulse Width Low 100 tBCKH Pulse Width High 50 tBLR BICK "" to LRCK Edge (Note: 17) 50 tLRB LRCK Edge to BICK "" (Note: 17) 50 tSDH SDTI Hold Time 50 tSDS SDTI Setup Time Control Interface Timing (I2C Bus): fSCL SCL Clock Frequency 4.7 tBUF Bus Free Time Between Transmissions 4.0 tHD:STA Start Condition Hold Time (prior to first clock pulse) 4.7 tLOW Clock Low Time 4.0 tHIGH Clock High Time 4.7 tSU:STA Setup Time for Repeated Start Condition 0 tHD:DAT SDA Hold Time from SCL Falling (Note: 18) 0.25 tSU:DAT SDA Setup Time from SCL Rising tR Rise Time of Both SDA and SCL Lines tF Fall Time of Both SDA and SCL Lines 4.0 tSU:STO Setup Time for Stop Condition 0 tSP Pulse Width of Spike Noise Suppressed by Input Filter Reset Timing tPD 150 PDN Pulse Width (Note: 19)
max 12.8 60 19.2 60 50 55
Units MHz % MHz % kHz % ns ns ns ns ns ns ns
100 1.0 0.3 50
kHz s s s s s s s s s s ns
ns
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ASAHI KASEI
[AK4702EQ]
Note: 17. BICK rising edge must not occur at the same time as LRCK edge. Note: 18. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. Note: 19. The AK4702 should be reset by PDN= "L" upon power up. Note: 20. I2C is a registered trademark of Philips Semiconductors.
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ASAHI KASEI
[AK4702EQ]
Timing Diagram
1/fCLK VIH VIL tCLKH tCLKL
dCLK=tCLKH x fCLK, tCLKL x fCLK
MCLK
1/fs VIH VIL
LRCK
tBCK VIH VIL tBCKH tBCKL
BICK
Clock Timing
LRCK tBLR tLRB
VIH VIL
BICK tSDS tSDH
VIH VIL
SDTI
VIH VIL
Serial Interface Timing
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ASAHI KASEI
[AK4702EQ]
tPD
PDN
VIL
Power-down Timing
VIH SDA VIL tBUF tLOW tR tHIGH tF tSP VIH SCL VIL tHD:STA Stop Start tHD:DAT tSU:DAT tSU:STA Start
I2C Bus mode Timing
tSU:STO Stop
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ASAHI KASEI
[AK4702EQ]
OPERATION OVERVIEW System Clock
The external clocks required to operate the DAC section of AK4702 are MCLK, LRCK and BICK. The master clock (MCLK) corresponds to 256fs or 384fs. MCLK frequency is automatically detected, and the internal master clock becomes 256fs. The MCLK should be synchronized with LRCK but the phase is not critical. Table 1 illustrates corresponding clock frequencies. All external clocks (MCLK, BICK and LRCK) should always be present whenever the DAC section of AK4702 is in the normal operating mode (STBY bit = "0"). If these clocks are not provided, the AK4702 may draw excess current because the device utilizes dynamically refreshed logic internally. The DAC section of AK4702 should be reset by STBY = "0" after threse clocks are provided. If the external clocks are not present, place the AK4702 in power-down mode (STBY bit = "1"). After exiting reset at power-up etc., the AK4702 remains in power-down mode until MCLK and LRCK are input. LRCK fs 32.0kHz 44.1kHz 48.0kHz MCLK 256fs 384fs 8.1920MHz 12.2880MHz 11.2896MHz 16.9344MHz 12.2880MHz 18.4320MHz Table 1. System clock example BICK 64fs 2.0480MHz 2.8224MHz 3.0720MHz
Audio Serial Interface Format
Data is shifted in via the SDTI pin using BICK and LRCK inputs. The DIF0 and DIF1 bits can select four formats in serial mode as shown in Table 2. In all modes, the serial data is MSB-first, 2's compliment format and is latched on the rising edge of BICK. Mode 2 can also be used for 16 MSB justified formats by zeroing the unused two LSBs. Mode 0 1 2 3 DIF1 0 0 1 1 DIF0 0 1 0 1 SDTI Format 16bit LSB Justified 18bit LSB Justified 18bit MSB Justified 18bit I2S Compatible BICK 32fs 36fs 36fs 36fs or 32fs Figure Figure 3 Figure 3 Figure 4 Figure 5 Default
Table 2. Audio Data Formats
LRCK BICK SDTI Mode 0 SDTI Mode 1
Don't care 15:MSB, 0:LSB Don't care 17:MSB, 0:LSB 17 16
15 14
0
Don't care
15 14
0
15
14
0
Don't care
17
16
15
14
0
Lch Data
Figure 3. Mode 0,1 Timing
Rch Data
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ASAHI KASEI
[AK4702EQ]
LRCK
BICK SDTI
17 16 17:MSB, 0:LSB
1
0
Don't care
17 16
1
0
Don't care
17
16
Lch Data
Figure 4. Mode 2 Timing
Rch Data
LRCK
BICK SDTI
17 16 17:MSB, 0:LSB
1
0
Don't care
17 16
1
0
Don't care
17
Lch Data
Figure 5. Mode 3 Timing
Rch Data
De-emphasis filter
A digital de-emphasis filter is available for 32, 44.1 or 48kHz sampling rates (tc = 50/15s) and is controlled by the DEM0 and DEM1 bits. DEM1 0 0 1 1 DEM0 0 1 0 1 Mode 44.1kHz OFF 48kHz 32kHz Default
Table 3. De-emphasis filter control
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ASAHI KASEI
[AK4702EQ]
Volume/Switch Control
The AK4702 has analog volume controls and switch matrixes designed primarily for SCART routing. Those are controlled via the control register as shown in, Table 4, Table 5, Table 7 and Table 8. (Please refer to the block diagram in figure 1.) DVOL1 0 0 1 1 DVOL0 0 1 0 1 Gain 0dB -6dB 2.44dB (Reserved) Output Level (at volume#1=0dB) 2Vrms 1Vrms 2.65Vrms (Reserved)
Table 4. Volume #0 (Digital Volume for DAC) L5 L4 L3 L2 1 0 0 0 1 0 0 0 1 0 0 0 0 1 1 1 ... ... ... ... 0 0 0 0 0 0 0 0 Note: Do not exceed 3Vrms as analog output. L1 1 0 0 1 ... 0 0 L0 0 1 0 1 ... 1 0 Gain +6dB +4dB +2dB 0dB (default) ... -60dB Mute
Table 5. Volume #1 (Analog Volume) TV1 0 0 1 1 TV0 0 1 0 1 Source of TVOUTL/R DAC VCRIN (default) Mute (Reserved)
Table 6. TVOUT Switch Configuration VOL 0 0 0 0 1 1 1 1 TV1 0 0 1 1 0 0 1 1 TV0 0 1 0 1 0 1 0 1 Source of MONOOUT DAC (L+R)/2 Bypass the DAC (L+R)/2 volume #1 DAC (L+R)/2 (Reserved) DAC (L+R)/2 Through the volume #1 VCRIN (L+R)/2 Mute (Reserved)
Table 7. MONOOUT Switch Configuration VCR1 0 0 1 1 VCR0 0 1 0 1 Source of VCROUTL/R DAC TVIN (default) Mute (Reserved)
Table 8. VCROUT Switch Configuration
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ASAHI KASEI
[AK4702EQ]
Zero-cross Detection and Offset Calibration
To minimize the click noise when changing the gain of volume#1, the AK4702 has a zero-cross detection and an offset calibration function. 1. Zero-cross detection function When the ZERO bit = "1", the zero-cross detection function is enabled. The gain of volume#1 changes at the first zero-cross point from the acknowledgement of a volume changing command or when the zero-cross is not detected within the time set by ZTM1-0 bits (256/fs to 2048/fs). The zero-cross counter is initialized whenever a gain is issued. The zero-cross is detected on L/R channels independently. To disable this function, set the ZERO bit to "0". ZERO: Zero-cross detection enable for volume#1 0 : Disable. The volume value changes immediately without zero-cross. 1 : Enable (default). The volume value changes at a zero-crossing point or when timeout (ZTM1-0 bit setting) occurs. The internal comparator for zero-cross detection has a small offset. Therefore, the gain of volume #1 may change due to a zero-cross timeout before the comparator-based zero-cross detection occurs. When the new gain value 1EH(-2dB) is written while the gain of both Lch and Rch are 1FH(0dB), if the Lch detects the zero-cross prior to Rch, only the gain of Lch changes to 1EH(-2dB) while Rch waits for a zero-cross. After that, if the gain is set to 1DH(-4dB) before either a zero-cross or zero-cross timeout, the Rch keeps the same value and changes from 1FH to 1DH at next zero-cross or timeout.
WR[Gain=1EH] WR[Gain=1DH] Zero-cross
Gain Registers
1FH
1EH
1DH
Lch Gain
1FH
1EH
1DH
Rch Gain
1FH
1DH
Timer (256/fs to2048/fs) Timeout; (may have click noise)
zero-cross timer initialized
Figure 6. Zero-cross Operation (ZERO= "1") 2. Offset calibration function Offset calibration is enabled when the CAL bit = "1". This function begins when the TVOUT source is switched to DAC after the STBY bit is changed to "0". It takes 1664/fs to execute the offset calibration cycle. During the offset calibration cycle, the analog outputs are muted. Once the offset calibration is executed, the calibration memory is held until PDN= "L" or the new calibration is executed. When the switch is changed from DAC to VCR during calibration, the calibration is discontinued, and resumed when TVOUT is switched back to DAC. If volume#1 gain is changed during calibration, the change takes place after calibration is complete.
Standby Mode
When the MUTE bit = "0" and the STBY bit = "1", the AK4702 is forced into TV-VCR loop through mode. In this mode, the sources of TVOUTL/R and MONOOUT are fixed to VCRINL/R, the sources of VCROUTL/R are fixed to TVINL/R respectively. The gain of volume#1 is fixed to 0dB. Since all registers are NOT initialized by STBY= "1", a register switch configuration requires standby mode (STBY= "0").
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ASAHI KASEI
[AK4702EQ]
System Reset and Power-down control
The AK4702 should be reset once by bringing PDN = "L" upon power-up. The AK4702 has several power-down modes. The PDN pin, MUTE bit and STBY bit control them as shown in Table 9 and Table 10. PDN pin: Power down pin. "H": Normal operation "L": Device power down. MUTE bit: Analog Mute bit. "1": Mute all analog outputs "0": Normal operation STBY bit : Standby bit. "1": Standby mode, DAC is powered down, volume is fixed to 0dB, the analog audio/video paths are fixed to TV-VCR loop-through. "0": Normal operation. After when the PDN pin is set to "H", the AK4702 is in standby mode and muted. To exit the mute and enter standby mode, set the MUTE bit to "0" and the STBY bit to "1". To use the DAC or change analog switches, set the STBY bit to "0". The DAC will power up and the internal timing starts clocking LRCK "" after exiting reset and power down states by MCLK. The AK4702 is in power-down mode until MCLK and LRCK are input.
Mode 0 1 2 3 4 Device power-down Standby and mute (default) Standby Mute Normal operation PDN pin "L" "H" "H" "H" "H" MUTE bit * 1 0 1 0 STBY bit * 1 1 0 0 MCLK, BICK, LRCK Not Needed Not Needed Not Needed Needed Needed DAC Powered Down Powered Down Powered Down Active Active Analog outputs GND GND fixed to TV-VCR loop-through GND Active Register control Not Available Available Available Available Available
Table 9. Power-down modes (audio)
Mode 0 1 2 Power-down Standby Normal operation
PDN pin "L" "H" "H"
STBY bit * 1 0
Video outputs Hi-z Active (Path is fixed) Active
TVFB, TVSB Hi-z Active Active
VCRSB Internally pulled down by 120kohm(typ) resister Active Active
Table 10. Power-down modes (video)
MS0424-E-00 - 20 -
2005/09
ASAHI KASEI
[AK4702EQ]
The Figure 7 shows an example of the system timing at the power-down and power-up by PDN pin.
PDN pin MUTE bit STBY bit "1" (default) "1" (default)
"Stand-by" "Mute" "Stand-by"
"0"
"1" "0"
"0" "1"
"1"
Clock in Data in
D/A Out (internal)
don't care (2) don't care "0" GD
normal operation Audio data "0" GD (1)
don't care (2) don't care
(1)
TV-Source select
fixed to VCR in(Loop-through)
VCR in (default)
DAC
VCR in
(4)
offset calibration
TV out
VCR in
VCR in
(3)
Notes: (1) The analog output corresponding to the digital input has a group delay, GD. (2) The external clocks (MCLK, BICK and LRCK) can be stopped in standby mode. (3) Please mute the analog outputs externally if click noise(3) adversely affects the system. (4) In case of the CAL bit = "1", the offset calibration is always executed when the source of TVOUT is switched to DAC after the STBY bit is changed to "0". To disable this function, set the CAL bit = "0". Figure 7. Power-down/up sequence example
MS0424-E-00 - 21 -
2005/09
ASAHI KASEI
[AK4702EQ]
Mode Control Interface
I2C-bus Control Mode The AK4702 supports the standard-mode I2C-bus (max: 100kHz). Then AK4702 doesn't support the fast-mode I2C-bus system (max: 400kHz).
1. WRITE Operations Figure 8 shows the data transfer sequence in I2C-bus mode. All commands are preceded by a START condition. A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 14). After the START condition, a slave address is sent. This address is 7 bits long followed by an eighth bit which is a data direction bit (R/W). The most significant seven bits of the slave address are fixed as "0010001". If the slave address match that of the AK4702, the AK4702 generates the acknowledge and the operation is executed. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse (Figure 15). A "1" for R/W bit indicates that the read operation is to be executed. A "0" indicates that the write operation is to be executed. The second byte consists of the address for control registers of the AK4702. The format is MSB first, and those most significant 3-bits are fixed to zeros (Figure 10). The data after the second byte contain control data. The format is MSB first, 8bits (Figure 11). The AK4702 generates an acknowledge after each byte has been received. A data transfer is always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition (Figure 14). The AK4702 can execute multiple one byte write operations in a sequence. After receipt of the third byte, the AK4702 generates an acknowledge, and awaits the next data again. The master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. After the receipt of each data, the internal address counter is incremented by one, and the next data is taken into next address automatically. If the address exceeds 08H prior to generating the stop condition, the address counter will "roll over" to 00H and the previous data will be overwritten. The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW (Figure 16) except for the START and the STOP condition.
S T A R T S T O P Data(n) A C K A C K Data(n+1) A C K A C K Data(n+x) A C K P
R/W= "0"
SDA
S
Slave Address A C K
Sub Address(n)
Figure 8. Data transfer sequence at the I2C-bus mode
0
0
1
0
0
0
1
R/W
Figure 9. The first byte
0
0
0
A4
A3
A2
A1
A0
Figure 10. The second byte
D7
D6
D5
D4
D3
D2
D1
D0
Figure 11. Byte structure after the second byte
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ASAHI KASEI
[AK4702EQ]
2. READ Operations Set R/W bit = "1" for READ operations. After transmission of data, the master can read the next address's data by generating an acknowledge instead of terminating the write cycle after the receipt the first data word. After the receipt of each data, the internal address counter is incremented by one, and the next data is taken into next address automatically. If the address exceeds 08H prior to generating the stop condition, the address counter will "roll over" to 00H and the previous data will be overwritten. The AK4702 supports two basic read operations: CURRENT ADDRESS READ and RANDOM READ. 2-1. CURRENT ADDRESS READ The AK4702 contains an internal address counter that maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either a read or write) was to address n, the next CURRENT READ operation would access data from the address n+1. After receipt of the slave address with R/W bit set to "1", the AK4702 generates an acknowledge, transmits 1byte data which address is set by the internal address counter and increments the internal address counter by 1. If the master does not generate an acknowledge to the data but generate the stop condition, the AK4702 discontinues transmission
S T A R T R/W= "1" S T O P Data(n+1) A C K A C K Data(n+2) A C K A C K Data(n+x) A C K P
SDA
S
Slave Address A C K
Data(n)
Figure 12. CURRENT ADDRESS READ 2-2. RANDOM READ Random read operation allows the master to access any memory location at random. Prior to issuing the slave address with the R/W bit set to "1", the master must first perform a "dummy" write operation. The master issues a start condition, slave address(R/W="0") and then the register address to read. After the register's address is acknowledge, the master immediately reissues the start condition and the slave address with the R/W bit set to "1". Then the AK4702 generates an acknowledge, 1-byte data and increments the internal address counter by 1. If the master does not generate an acknowledge to the data but generate the stop condition, the AK4702 discontinues transmission.
S T A R T R/W= "0" S T A R T S A C K Slave Address A C K R/W= "1" S T O P Data(n+1) A C K A C K A C K Data(n+x) A C K P
SDA
S
Slave Address A C K
Sub Address(n)
Data(n)
Figure 13. RANDOM ADDRESS READ
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ASAHI KASEI
[AK4702EQ]
SDA
SCL S start condition P stop condition
Figure 14. START and STOP conditions
DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER S clock pulse for acknowledgement
1
2
8
9
START CONDITION
Figure 15. Acknowledge on the I2C-bus
SDA
SCL
data line stable; data valid
change of data allowed
Figure 16. Bit transfer on the I2C-bus
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ASAHI KASEI
[AK4702EQ]
Register Map
Addr 00H 01H 02H 03H 04H 05H 06H 07H 08H Register Name Control Switch Main Volume Zerocross Video Switch Video output enable Video Volume/Clamp S/F Blanking control S/F Blanking monitor D7
DEM1 VMUTE 0 0 VRF1 CIO 0 SBIO1 0
D6
DEM0 MMON 0 0 VRF0 TVFB VCLP1 SBIO0 0
D5
DIF1 VCR1 L5 CAL VVCR2 VCRC VCLP0 SBV1 0
D4
DIF0 VCR0 L4 DVOL1 VVCR1 VCRV 0 SBV0 0
D3
0 MONO L3 DVOL0 VVCR0 TVB CLAMP1 SBT1 0
D2
0 VOL L2 ZERO VTV2 TVG CLAMP0 SBT0 FVCR
D1
MUTE TV1 L1 ZTM1 VTV1 TVR VVOL1 FB1 SVCR1
D0
STBY TV0 L0 ZTM0 VTV0 TVV VVOL0 FB0 SVCR0
When the PDN pin goes "L", the registers are initialized to their default values. While the PDN="H", all registers can be accessed. Do not write any data to the register over 08H.
Register Definitions
Addr 00H Register Name Control R/W default 0 1 1 1 D7 DEM1 D6 DEM0 D5 DIF1 D4 DIF0 R/W 0 0 1 1 D3 0 D2 0 D1 MUTE D0 STBY
STBY: Standby control 0 : Normal Operation 1 : Standby Mode(default). All registers are not initialized. DAC : powered down and timings are reset. Gain of Volume#1 : fixed to 0dB, Source of TVOUT : fixed to VCRIN, Source of VCROUT : fixed to TVIN, Source of MONOOUT : fixed to VCRIN, Source of TVVOUT : fixed to VCRVIN(or Hi-Z), Source of TVRC : fixed to VCRRC(or Hi-Z), Source of TVG : fixed to VCRG(or Hi-Z), Source of TVB : fixed to VCRB(or Hi-Z), Source of VCRVOUT : fixed to TVVIN(or Hi-Z), Source of VCRC : fixed to Hi-Z or VSS(controlled by CIO bit). MUTE: Audio output control 0 : Normal Operation 1 : ALL Audio outputs to GND (default) DIF1-0: Audio data interface format control 00 : 16bit LSB Justified 01 : 18bit LSB Justified 10 : 18bit MSB Justified 11 : 18bit I2S Compatible (Default) DEM1-0: De-emphasis Response Control 00 : 44.1kHz 01 : off (Default) 10 : 48kHz 11 : 32kHz
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ASAHI KASEI
[AK4702EQ]
Addr 01H
Register Name Switch R/W default
D7 VMUTE 1
D6
MMON
D5 VCR1 0
D4 VCR0 1 R/W
D3
MONO
D2
VOL
D1 TV1 0
D0 TV0 1
1
0
1
TV1-0: TVOUT source switch 00 : DAC 01 : VCRIN (Default) 10 : MUTE 11 : (Reserved) VOL: Source select for MONOOUT 0 : Bypass the volume (fixed to DAC out) 1 : Through the volume (Default) MONO: Mono select for TVOUT 0 : Stereo. (Default) 1 : Mono. (L+R)/2 VCR1-0: VCROUT source switch 00 : DAC 01 : TVIN (Default) 10 : MUTE 11 : (Reserved) MMON: Mute of MONOIN input 0 : Add the MONOIN 1 : Mute the MONOIN (default) VMUTE: Mute switch for volume#1 0 : Normal operation 1 : Mute the volume#1 (Default)
Addr 02H
Register Name Main Volume R/W default
D7 0 0
D6 0 0
D5 L5 0
D4 L4 R/W 1
D3 L3 1
D2 L2 1
D1 L1 1
D0 L0 1
L5-0: Volume#1 control Those registers control both Lch and Rch of Volume#1. 111111 to 100011 : (Reserved) 100010 : Volume gain = +6dB 100001 : Volume gain = +4dB 100000 : Volume gain = +2dB 011111 : Volume gain = +0dB (default) 011110 : Volume gain = -2dB ... 000011 : Volume gain = -56dB 000010 : Volume gain = -58dB 000001 : Volume gain = -60dB 000000 : Volume gain = Mute
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ASAHI KASEI
[AK4702EQ]
Addr 03H
Register Name Zerocross R/W default
D7 0 0
D6
0
D5 CAL 1
D4 DVOL1 R/W 0
D3 DVOL0 0
D2 ZERO 1
D1 ZTM1 1
D0 ZTM0 1
0
ZTM1-0: The time length control of zero-cross timeout 00 : typ. 256/fs 01 : 512/fs 10 : 1024/fs 11 : 2048/fs (default) ZERO: Zero-cross detection enable for volume control#1 0 : Disable The volume value changes immediately without zero-cross. 1 : Enable (default) The volume value changes when timeout or zero-cross before timeout. This function is disabled when STBY= "1". DVOL1-0: Digital volume control for DAC (Volume#0) 00 : 0dB 01 : -6dB 10 : +2.44dB 11 : (Reserved) CAL: Offset calibration Enable 0 : Offset calibration disable. 1 : Offset calibration enable(default)
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2005/09
ASAHI KASEI
[AK4702EQ]
Addr 04H
Register Name Video Switch R/W default
D7 VRF1 1
D6 VRF0 0
D5 VVCR2 0
D4 VVCR1 1 R/W
D3 VVCR0 1
D2 VTV2 1
D1 VTV1 0
D0 VTV0 0
VTV0-2: selector for TV video output Mode VTV2-0 TVVOUT TVRC TVG Shutdown 000 Hi-Z Hi-Z Hi-Z Encoder CVBS Encoder R Encoder G Encoder CVBS 001 ENCV ENCRC ENCG or RGB Encoder Encoder Encoder Y/C 1 010 Luminance Chrominance Hi-Z ENCV ENCRC Encoder Encoder Encoder Y/C 2 011 Luminance Chrominance Hi-Z ENCY ENCC VCR VCR CVBS/Y VCR R/C VCR G 100 (default) VCRVIN VCRRC VCRG TV CVBS/Y Hi-Z Hi-Z TV CVBS 101 TVVIN (reserved) 110 (reserved) 111 Table 11. TV video output (see note) VVCR0-2: selector for VCR video output Mode VVCR2-0 Shutdown 000 Encoder CVBS 001 or Y/C 1 Encoder CVBS 010 or Y/C 2 TV CVBS 011 (default) VCR (reserved) (reserved) (reserved) 100 101 110 111
TVB Hi-Z Encoder B ENCB Hi-Z
Hi-Z VCR B VCRB Hi-Z -
VCRVOUT VCRC Hi-Z Hi-Z Encoder CVBS/Y Encoder Chrominance ENCV ENCRC Encoder CVBS/Y Encoder Chrominance ENCY ENCC TV CVBS Hi-Z TVVIN VCR CVBS/Y VCR R/C VCRVIN VCRRC Table 12. VCR video output (see note)
VRF0-1: selector for RF video output Mode Encoder CVBS1 Encoder CVBS2 VCR (default) Shutdown
VRF1-0 00 01 10 11
RF CVBS Encoder CVBS1 ENCV Encoder CVBS2 ENCG (Note: 22) VCR VCRVIN Hi-Z
Table 13. RF video output (see note) Note: 21: When input the video signal via ENCRC or VCRRC pin, set CLAMP1-0 bits respectively. Note: 22 When VTV2-0="001", TVG="1" and VRF1-0="01", RFV output is same as TVG (Encoder G).
MS0424-E-00 - 28 -
2005/09
ASAHI KASEI
[AK4702EQ]
Addr 05H
Register Name
output enable
D7
CIO
D6
TVFB 0
D5
VCRC
D4
VCRV
D3
TVB
D2
TVG
D1
TVR
D0
TVV
R/W default
R/W 0 0 0 0 0 0 0
Each video outputs can be set to Hi-Z individually. TVV : TVVOUT output control TVR : TVRCOUT output control TVG : TVGOUT output control TVB : TVBOUT output control VCRV : VCRVOUT output control VCRC : VCRC output control TVFB : TVFB output control 0 : Hi-Z (default) 1 : Active. When CIO= "1", the VCRC pin is connected to GND even if VCRC= "0". When CIO= "0", the VCRC pin follows the setting of VCRC bit. CIO: VCR Chrominance I/O control 0 : Active (output). 1 : Connected to GND CIO 0 0 1 1 VCRC State of VCRC pin 0 Hi-z (default) 1 Active 0 Connected to GND 1 Connected to GND Table 14 VCRC output control
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2005/09
ASAHI KASEI
[AK4702EQ]
Addr 06H
Register Name Video Volume R/W default
D7
0
D6
VCLP1 0
D5
VCLP0
D4
0
D3
CLAMP1
D2
CLAMP0
D1
VVOL1
D0
VVOL0
R/W 0 0 0 0 1 0 0
VVOL1-0: RGB video gain control VVOL1 0 0 1 1 VVOL0 0 1 0 1 Gain Output level (Typ. @Input=0.7Vpp) +6dB 1.4Vpp (default) +7.2dB 1.6Vpp +8.2dB 1.8Vpp +9.1dB 2.0Vpp Table 15. RGB gain
CLAMP1 : Encoder R/Chroma (ENCRC pin)input clamp control 0 : DC restore clamp active (for RED signal. default) 1 : Biased (for Chroma signal.) CLAMP0 : VCR R/C (VCRC pin)input clamp control 0 : DC restore clamp active (for RED signal) 1 : Biased (for Chroma signal. default.) VCLP1-0 : DC restore source control VCLP1 0 0 1 1 VCLP0 Sync Source of DC Restore 0 ENCV (default) 1 ENCY 0 VCRVIN 1 (Reserved) Table 16. DC restore source control
MS0424-E-00 - 30 -
2005/09
ASAHI KASEI
[AK4702EQ]
Addr 07H
Register Name S/F Blanking R/W default
D7 SBIO1 0
D6 SBIO0
0
D5 SBV1 0
D4 SBV0 R/W 0
D3 SBT1 0
D2 SBT0 0
D1 FB1 0
D0 FB0 0
FB1-0: TV Fast Blanking output control (for TVFB) FB1 0 0 1 1 TV FB Output Level 0V (default) 4V Same as VCR FB input (4V/0V) (Reserved) (note: minimum load is 150ohm) Table 17. TV Fast Blanking output FB0 0 1 0 1
SBT1-0: TV Slow Blanking output control (for TVSB) SBT1-0 do not work correctly when VP<11.4V SBT1 0 0 1 1 Slow Blanking Output Level <2V (default) 5V<, <7V (Reserved) 10V< (note: minimum load is 10kohm) Table 18. TV Slow Blanking output SBT0 0 1 0 1
SBV1-0: VCR Slow Blanking output control (for VCRSB) SBV1-0 do not work correctly when VP<11.4V SBV1 0 0 1 1 Slow Blanking Output Level <2V (default) 5V<, <7V (Reserved) 10V< (note: minimum load is 10kohm) Table 19. VCR Slow Blanking output SBV0 0 1 0 1
SBIO1-0: TV/VCR Slow Blanking I/O control SBIO1-0 do not work correctly when VP<11.4V SBIO1 0 0 1 1 SBIO0 0 1 0 1 VCR Slow Blanking Direction TV Slow Blanking Direction Output Output (Controlled by SBV1,0) (Controlled by SBT1,0) (Reserved) (Reserved) Input Output (Stored in SVCR1,0) (Controlled by SBT1,0) Input Output (Stored in SVCR1,0) (Same output as VCR SB) Table 20. TV/VCR Slow Blanking output
(default)
MS0424-E-00 - 31 -
2005/09
ASAHI KASEI
[AK4702EQ]
Addr 08H
Register Name SB/FB Monitor R/W default
D7 0 0
D6 0
0
D5 0 0
D4 0 READ 0
D3 0 0
D2 FVCR 0
D1 SVCR1 0
D0 SVCR0 0
SVCR1-0: VCR Slow blanking status monitor Those bits reflect the voltage at VCRSB pin for both Input/Output modes SVCR1-0 do not work correctly when VP<11.4V SVCR1 SVCR0 VCRSB Level 0 0 < 2V 0 1 4.5 to 7V 1 0 (Reserved) 1 1 9.5< Table 21. VCR Slow Blanking monitor FVCR: VCR Fast blanking input level monitor This bit is enabled when TVFB bit = "1". FVCR VCRFB Input Level 0 <0.4V 1 1 V< Table 22. VCR Fast Blanking monitor (Typical threshold is 0.7V) Changes to the 08H status can be monitored via the INT pin. The INT pin is the open drain output and goes "L" for 2usec(typ.) when the status of 08H is changed. This pin should be connected to VD (typ. 5V) through 10kohm resister.
MS0424-E-00 - 32 -
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ASAHI KASEI
[AK4702EQ]
SYSTEM DESIGN
RFV MONOOUT
CVBS Audio MONO
RF Mod
Phono
TVOUTL TVOUTR TVRC TVG TVB TVFB TVVOUT CVBS/Y Y C Encoder R/C G/CVBS B MCLK MPEG Decoder BICK LRCK SDATA SCK SDA PDN Interrupt ENCV ENCY ENCC ENCRC ENCGV ENCB VCRVIN MCLK BICK LRCK SDATA SCK SDA PDN INT VCRRC VCRC VCRG VCRB VCRINL Micro Processor VCRINR VCRVOUT VCROUTL VCROUTR VCRSB TVVIN TVINL TVINR TVSB VCRFB
Audio L Audio R R/C G B Fast Blank Y/CVBS Y/CVBS Audio L Audio R Slow Blank Fast Blank Y/CVBS R/C TV SCART
G B Audio L Audio R Y/CVBS Audio L Audio R Slow Blank VCR SCART
Figure 17. Typical Connection Diagram
MS0424-E-00 - 33 -
2005/09
ASAHI KASEI
[AK4702EQ]
1. Grounding and Power Supply Decoupling
VD, VP, VVD1, VVD2, VSS and VVSS should be supplied from analog supply unit and be separated from system digital supply. Decoupling capacitor, especially the 0.1F ceramic capacitor for high frequency noise should be placed as near to VD (VP, VVD1, VVD2) as possible.
2. Voltage Reference
Each VCOM is a signal ground of this chip. An electrolytic capacitor 10F parallel with a 0.1F ceramic capacitor attached to VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from VCOM pin. All signals, especially clocks, should be kept away from VCOM pins in order to avoid unwanted coupling into the AK4702.
3. Analog Audio Outputs
The analog outputs are also single-ended and centered on 5.6V(Typ.). The output signal range is typically 2Vrms (typ@VD=5V). The internal switched-capacitor filter and continuous-time filter attenuate the noise generated by the delta-sigma modulator beyond the audio pass band. Therefore, any external filters are not required for typical application. The output voltage is a positive full scale for 7FFFFFH (@18bit) and a negative full scale for 800000H (@18bit). The ideal output is 5.6V(Typ.) for 000000H (@18bit). The DC voltage on analog outputs are eliminated by AC coupling.
MS0424-E-00 - 34 -
2005/09
ASAHI KASEI
[AK4702EQ]
4. External Circuit Example
Analog Audio Input pin
300ohm MONOIN TVINL/R VCRINL/R
(Cable)
0.47F
Analog Audio Output pin
MONOOUT TVOUTL/R VCROUTL/R
10F
300ohm
(Cable)
Total > 4.5kohm
Analog Video Input pin
ENCV, ENCY, VCRVIN, TVVIN, ENCRC, ENCC, VCRRC, ENCG, VCRG, ENCB, VCRB
75ohm
(Cable) 75ohm
0.1F
Analog Video Output pin (Except RFV pin)
TVVOUT, TVRC TVG, TVR VCRVOUT, VCRC 75ohm
(Cable) max 400pF 75ohm
max 15pF
Analog Video Output pin (RFV pin) The AK4702 does not have 75ohm driver. Please use an external buffer if the input impedance of the RF modulator is less than 20kohm.
RFV Buffer Zin>20kohm RF Modulator
Max 15pF
MS0424-E-00 - 35 -
2005/09
ASAHI KASEI
[AK4702EQ]
Slow Blanking pin
TVSB VCRSB 400ohm
(max 500ohm)
(Cable) max 3nF (with 400ohm) min: 10k ohm
Fast Blanking Input pin
VCRFB 75ohm (Cable) 75ohm
Fast Blanking Output pin
75ohm TVFB (Cable) 75ohm
MS0424-E-00 - 36 -
2005/09
ASAHI KASEI
[AK4702EQ]
PACKAGE
48pin LQFP(Unit:mm)
9.0 0.2 7.0 36 25 24 9.0 0.2
1.70Max 0.13 0.13 1.40 0.05
37
48 1 0.22 0.08 12
13
7.0
0.145 0.05 0.5 0.10 M
0 10
0.10
0.5 0.2
Package & Lead frame material
Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder (Pb free) plate
MS0424-E-00 - 37 -
2005/09
ASAHI KASEI
[AK4702EQ]
MARKING
AK4702EQ XXXXXXX
1
XXXXXXXX: Date code identifier
Revision History
Date (YY/MM/DD) 05/09/20 Revision 00 Reason First Edition Page Contents
MS0424-E-00 - 38 -
2005/09
ASAHI KASEI
[AK4702EQ]
IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.
MS0424-E-00 - 39 -
2005/09

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